This weekend I got a chance to spend some time thinking about life and a variety of concerns. My church has a General Conference every 6 months and this last weekend was one such conference. During these conferences the church leaders share their thoughts and give direction and guidance to help people to live better lives where they can contribute more to the church and society at large. As the weekend went on, I shared a couple of quotes from the procedings that stood out to me on my twitter account.
Yesterday, I managed to put together the in-class demo I discussed previously. In this post I’d like to give a brief explanation of what I showed and how it demonstrates the proper use of SystemVerilog to describe a finite state machine (FSM). What I saw many students doing in their 3rd lab, was to use an English language description of the behavior they wanted that they translated directly to behavioral SystemVerilog.
In grading some labs this week, I noticed a trend among my students to create something that was essentially a finite state machine (FSM) without actually explicitly making a finite state machine in their verilog description. Typically a FSM has 3 parts, a state register, next state logic, and output logic. The only part of the FSM that should be sequential logic is the state register while the other parts should be purely combinational logic.
Today I came across a blog post from a developer who describes a project he worked on that failed spectacularly. This project was a web database query to sort real estate brokers for an insurance company. If you want to see the results of the project in the way the original author intended, then you should visit the link above. It turns out that the insurance company provides the contact info of real estate brokers solely to collect a referral fee for that service.
Just a quick note on emailing professors. If you are asking for help or corrections on an assignment, you should send those kinds of emails ahead of time. Also, if you expect the professor to have complete knowledge of the problems in the book on the weekend, then you’re going to have a bad time. Every semester, I’ve had questions about problems in the book, and the student will email me the problem number in question rather than describe what the problem is.
I bought my first iPhone 2 years ago in October of 2011. I got the 5th iPhone then, the one called the iPhone 4S (or force for short). Two years have passed and I was eligible for a subsidized upgrade on the 7th iPhone, which they call iPhone 5S (is that SS or 55?). I decided I wanted to get the new upgrade, so I went ahead and ordered one online just after midnight when they went on sale.
Over the last year, I advised 5 undergraduate students on a couple research projects. One of them included the development of tutorials and lab assignments for a new class, but didn’t have a goal of publishing an academic paper. This student did a good job, and added on a persistance of vision display to a combat robot’s spinning arm that wouldn’t have otherwise been there. The other main project involved the rest of my research students.
I recently discovered a new feature that comes with Jekyll bootstrap, but I’m unsure whether it is only in JB, or if it comes by default with Jekyll. There is a Rakefile (which is sort of like a Makefile, but written in Ruby) that includes a few nice functions. The one I discovered most recently allows you to create a new blog post complete with the YAML frontmatter and the proper file name for Jekyll to do the right thing with.
This week I met with each of the students in my MicroPs class and discussed their lab assignment. The first lab assignment was primarily soldering components onto their PCB and verifying that all of the components worked. As part of these lab interviews, I get to ask each student a question about their project to try to test their knowledge. One thing I noticed is that many of the students didn’t own their project as fully as I would like.
In my embedded systems class, I decided it would be helpful to start with a review of SystemVerilog to hopefully keep the students from falling into the common pitfalls that come with using hardware description languages to describe hardware. Some important topics I touched on include the “proper” way to describe a Finite State Machine using SystemVerilog. As a part of that, I made sure to point out the kinds of things that you can do in SystemVerilog to accidentally describe sequential logic when you actually intended for the circuit to be combinational.