Yesterday, I managed to put together the in-class demo I discussed previously. In this post I’d like to give a brief explanation of what I showed and how it demonstrates the proper use of SystemVerilog to describe a finite state machine (FSM).
What I saw many students doing in their 3rd lab, was to use an English language description of the behavior they wanted that they translated directly to behavioral SystemVerilog.
In grading some labs this week, I noticed a trend among my students to create something that was essentially a finite state machine (FSM) without actually explicitly making a finite state machine in their verilog description. Typically a FSM has 3 parts, a state register, next state logic, and output logic. The only part of the FSM that should be sequential logic is the state register while the other parts should be purely combinational logic.