In my embedded systems class, I decided it would be helpful to start with a review of SystemVerilog to hopefully keep the students from falling into the common pitfalls that come with using hardware description languages to describe hardware. Some important topics I touched on include the “proper” way to describe a Finite State Machine using SystemVerilog. As a part of that, I made sure to point out the kinds of things that you can do in SystemVerilog to accidentally describe sequential logic when you actually intended for the circuit to be combinational.