I recently gave a problem on the final in E85. The students didn’t do too well on it overall, so I wanted to post the problem and solution in an effort to make more resources available for people learning basic cache behaviors. First of all, I need to introduce the piece of ARM assembly being used since it is the basis for a number of questions.
FUNC: 0x0044 SUBS R0, R0, #3 0x0048 BLT DONE 0x004C STR LR, [SP, #-4]!

This semester has been extremely exciting. In particular, E85 has been updated from MIPS to use the ARM v7 instructions set. This has been a good experience for me despite some difficulties and a few moments of intensity where I wasn’t sure things would come together in time. In doing this, I’ve come to learn a lot about the ARM ISA, and I’ve decided I like it a lot. In particular, I think it strikes a reasonably good balance between RISC and CISC instructions where there are a couple nice addressing modes for stack manipulation that aren’t quite RISC, but are close enough.

Yesterday, I managed to put together the in-class demo I discussed previously. In this post I’d like to give a brief explanation of what I showed and how it demonstrates the proper use of SystemVerilog to describe a finite state machine (FSM).
What I saw many students doing in their 3rd lab, was to use an English language description of the behavior they wanted that they translated directly to behavioral SystemVerilog.

In grading some labs this week, I noticed a trend among my students to create something that was essentially a finite state machine (FSM) without actually explicitly making a finite state machine in their verilog description. Typically a FSM has 3 parts, a state register, next state logic, and output logic. The only part of the FSM that should be sequential logic is the state register while the other parts should be purely combinational logic.

In my embedded systems class, I decided it would be helpful to start with a review of SystemVerilog to hopefully keep the students from falling into the common pitfalls that come with using hardware description languages to describe hardware. Some important topics I touched on include the “proper” way to describe a Finite State Machine using SystemVerilog. As a part of that, I made sure to point out the kinds of things that you can do in SystemVerilog to accidentally describe sequential logic when you actually intended for the circuit to be combinational.

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