I recently gave a problem on the final in E85. The students didn’t do too well on it overall, so I wanted to post the problem and solution in an effort to make more resources available for people learning basic cache behaviors. First of all, I need to introduce the piece of ARM assembly being used since it is the basis for a number of questions.
FUNC: 0x0044 SUBS R0, R0, #3 0x0048 BLT DONE 0x004C STR LR, [SP, #-4]!
This semester has been extremely exciting. In particular, E85 has been updated from MIPS to use the ARM v7 instructions set. This has been a good experience for me despite some difficulties and a few moments of intensity where I wasn’t sure things would come together in time. In doing this, I’ve come to learn a lot about the ARM ISA, and I’ve decided I like it a lot. In particular, I think it strikes a reasonably good balance between RISC and CISC instructions where there are a couple nice addressing modes for stack manipulation that aren’t quite RISC, but are close enough.
This semester I am teaching a project-based class that has almost no formal instruction by the professor. Instead of providing close direction, I am attempting to give the students more autonomy and control over their learning and the things they will get out of the class. This presents a number of difficulties, and I plan to discuss them as the semester proceeds. Today, I’d like to say something about student-run class sessions, which will happen for the first time in my class next week.
Today I had the fortunate presence of mind to record videos for a couple of my students’ lab projects that I found particularly interesting. In this post I’ll go ahead and embed these videos for anyone interested in watching them. To explain briefly, the assignment was to use assembly programming for the PIC 32 microcontroller to have a speaker produce a song. Optionally, students were allowed to play a song of their choosing after putting that song in the program memory.
Yesterday, I managed to put together the in-class demo I discussed previously. In this post I’d like to give a brief explanation of what I showed and how it demonstrates the proper use of SystemVerilog to describe a finite state machine (FSM).
What I saw many students doing in their 3rd lab, was to use an English language description of the behavior they wanted that they translated directly to behavioral SystemVerilog.
In grading some labs this week, I noticed a trend among my students to create something that was essentially a finite state machine (FSM) without actually explicitly making a finite state machine in their verilog description. Typically a FSM has 3 parts, a state register, next state logic, and output logic. The only part of the FSM that should be sequential logic is the state register while the other parts should be purely combinational logic.
Just a quick note on emailing professors. If you are asking for help or corrections on an assignment, you should send those kinds of emails ahead of time. Also, if you expect the professor to have complete knowledge of the problems in the book on the weekend, then you’re going to have a bad time. Every semester, I’ve had questions about problems in the book, and the student will email me the problem number in question rather than describe what the problem is.
This week I met with each of the students in my MicroPs class and discussed their lab assignment. The first lab assignment was primarily soldering components onto their PCB and verifying that all of the components worked. As part of these lab interviews, I get to ask each student a question about their project to try to test their knowledge. One thing I noticed is that many of the students didn’t own their project as fully as I would like.
In my embedded systems class, I decided it would be helpful to start with a review of SystemVerilog to hopefully keep the students from falling into the common pitfalls that come with using hardware description languages to describe hardware. Some important topics I touched on include the “proper” way to describe a Finite State Machine using SystemVerilog. As a part of that, I made sure to point out the kinds of things that you can do in SystemVerilog to accidentally describe sequential logic when you actually intended for the circuit to be combinational.
A couple weeks ago, I received a call asking me to teach an extra class this semester (Fall 2013). This was the result of a last minute change out of my control that required an extra instructor to come in on the class. I decided to say “yes” because I have taught the course before, and I was probably the most natural fit to fill in at the last minute. Unfortunately, this caused my other class to have to change lecture time, and subsequently caused a whole bunch of scheduling issues with many students in the class who were taking classes at the same time.